M12S16161A_07 Datasheet, PDF (15/29 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

ESMT
Page Read & Write Cycle at Same Bank @ Burst Length=4
M12S16161A
0
1
2
CLOCK
CKE
3
4
5
6
7
8
9
10 11
12 13
14
15 16
17 18
19
HIGH
CS
RAS
tRCD
*Note2
CAS
ADDR
Ra
Ca0
Cb0
Cc0
Cd0
BA
A10/AP
Ra
CL=2
DQ
CL=3
WE
DQM
Qa0 Qa1 Qb0 Qb1 Qb2
Qa0 Qa1 Qb0 Qb1
*Note1
tRDL
Dc0 Dc1 Dd0 Dd1
Dc0 Dc1 Dd0 Dd2
tCDL
*Note3
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note :1.To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus
contention.
2.Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3.DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.1
15/29