M12S16161A_07 Datasheet, PDF (24/29 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

ESMT
M12S16161A
Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18 19
CLOCK
CKE
tSS
*Note1
*Note2
tSS
tSS
*Note3
CS
RAS
CAS
ADDR
BA
Ra
Ca
A10/AP
DQ
WE
DQM
Ra
tSHZ
Qa0 Qa1 Qa2
Pr ech ar ge
Power-Down
Entry
Row Active
Precharge
Power-Down
Exit
Active
Power-down
Entry
Read
Active
Power-down
Exit
Precharge
: Don't care
*Note :1.Both banks should be in idle state prior to entering precharge power down mode.
2.CKE should be set high at least 1CLK+tss prior to Row active command.
3.Can not violate minimum refresh specification. (32ms)
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.1
24/29