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M12S16161A_07 Datasheet, PDF (1/29 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM
ESMT
SDRAM
M12S16161A
512K x 16Bit x 2Banks
Synchronous DRAM
FEATURES
z JEDEC standard 2.5V power supply
z LVTTL compatible with multiplexed address
z Dual banks operation
z MRS cycle with address key programs
- CAS Latency (2 & 3 )
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
z All inputs are sampled at the positive going edge of the
system clock
z Burst Read Single-bit Write operation
z DQM for masking
z Auto & self refresh
z 32ms refresh period (2K cycle)
GENERAL DESCRIPTION
The M12S16161A is 16,777,216 bits synchronous high
data rate Dynamic RAM organized as 2 x 524,288 words by
16 bits, fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
ORDERING INFORMATION
Part NO.
M12S16161A-7TG
M12S16161A-7BG
MAX Freq.
143MHz
143MHz
PACKAGE COMMENTS
50 TSOP(II) Pb-free
VFBGA
Pb-free
PIN CONFIGURATION (TOP VIEW)
VDD
1
DQ0
2
DQ1
3
VSSQ
4
DQ2
5
DQ3
6
VDDQ
7
DQ4
8
DQ5
9
VSSQ
10
DQ6
11
DQ7
12
VDDQ
13
LDQM 14
WE
15
CAS
16
RAS
17
CS
18
BA
19
A10/AP 20
A0
21
A1
22
A2
23
A3
24
VDD
25
50 VSS
49 DQ15
48 DQ14
47 VSSQ
46 DQ13
45 DQ12
44 VDDQ
43 DQ11
42 DQ10
41 VSSQ
40 DQ9
39 DQ8
38 VDDQ
37 N.C/RFU
36 UDQM
35 CLK
34 CKE
33 N.C
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 VSS
50PIN TSOP(II)
(400mil x 825mil)
(0.8 mm PIN PITCH)
1
2
3
4
5
6
7
A
VSS DQ15
DQ0 VDD
B
DQ14 VSSQ
VDDQ DQ1
C
DQ13 VDDQ
VSSQ DQ2
D
DQ12 DQ11
DQ4 DQ3
E
DQ10 VSSQ
VDDQ DQ5
F
DQ9 VDDQ
VSSQ DQ6
G
DQ8 NC
NC
DQ7
H
NC
NC
J
NC UDQM
NC
NC
LDQM WE
K
NC
CLK
L
CKE
NC
RAS CAS
NC
CS
M
A11
A9
NC
NC
N
A8
A7
A0
A10
P
A6
A5
A2
A1
R
VSS
A4
A3 VDD
60 Ball VFBGA
(6.4x10.1mm)
(0.65mm ball pitch)
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.1
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