M12S16161A_07 Datasheet, PDF (10/29 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

ESMT
SIMPLIFIED TRUTH TABLE
M12S16161A
Register
Refresh
COMMAND
Mode Register Set
Auto Refresh
Entry
Self Refresh
Exit
Bank Active & Row Addr.
Read &
Column Address
Write & Column
Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Burst Stop
Precharge
Bank Selection
Both Banks
Clock Suspend or
Active Power Down
Entry
Exit
Precharge Power Down Mode
Entry
Exit
DQM
No Operation Command
CKEn-1 CKEn _{CS RAS CAS WE} DQM BA A10/AP A9~A0 Note
H
XLL
L
L
X
OP CODE
1,2
H
H
L
L
L
L
H
X
X
3
3
LH
H
H
L
HHX
X
X
X
3
X
3
H
XLL
H
H
X V Row Address
H
XLH
L
H
XV
L ^{Column 4}
Address
H (A0~A7) ^4,5
H
XLH
L
L
XV
L ^Column 4
H
Address
(A0~A7)
4,5
H
XLH
H
L
X
X
6
H
XLL
H
L
X
V
X
L
H
X
4
4
HX
X
X
H
L
L
V
V
V
X
X
L
HXX
X
X
X
H
L
H
L
X
H
X
H
X
H
X
L
H
H
L
X
V
X
V
X
V
X
X
H
X
V
X
7
H
HX
X
X
H
X
L
H
H
H
X
X
(V= Valid, X= Don’t Care, H= Logic High , L = Logic Low)
Note:
1. OP Code: Operation Code
A0~ A10/AP, BA: Program keys.(@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto / self refresh can be issued only at both banks idle state.
4. BA: Bank select address.
If “Low”: at read, write, row active and precharge, bank A is selected.
If “High”: at read, write, row active and precharge, bank B is selected.
If A10/AP is “High” at row precharge, BA ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read /write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but
makes
Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.1
10/29