M12S16161A_07 Datasheet, PDF (17/29 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

ESMT
Page Write Cycle at Different Bank @Burst Length = 4
M12S16161A
0
1
2
CLOCK
3
4
5
6
7
8
9
10 11 12 13 14
15 16 17 18
19
CKE
HIGH
CS
RAS
CAS
ADDR
RAa
CAa _RBb
CBb
BA
CAc
CBd
*Note2
A10/AP
RAa
DQ
WE
DQM
RBb
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1
tCDL
tRDL
*Note1
Row Active
(A-Bank)
Row Active
(B-Bank)
Write
(A-Bank)
Write
(B-Bank)
Write
(A-Bank)
Write
(B-Bank)
Precharge
(Both Banks)
: Don't care
*Note: 1.To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2.To interrupt burst write by row precharge, both the write and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.1
17/29