M12S16161A_07 Datasheet, PDF (4/29 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

ESMT
M12S16161A
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70 °C
Parameter
Symbol
Test Condition
CAS
Latency
Operating Current
(One Bank Active)
ICC1
Burst Length = 1
tRC ≥ tRC (min), tCC ≥ tCC (min), IOL= 0mA
Precharge Standby
Current in power-down
mode
ICC2P
ICC2PS
CKE ≤ VIL(max), tCC =15ns
CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞
Precharge Standby
Current in non
power-down mode
ICC2N
ICC2NS
CKE ≥ VIH(min), CS ≥ VIH(min), tCC =15ns
Input signals are changed one time during 30ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
Active Standby Current
in power-down mode
ICC3P
ICC3PS
CKE ≤ VIL(max), tCC =15ns
CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞
Active Standby Current
in non power-down
mode
(One Bank Active)
ICC3N
ICC3NS
CKE ≥ VIH(min), CS ≥ VIH(min), tCC=15ns
Input signals are changed one time during 30ns
CKE ≥ VIH (min), CLK ≤ VIL(max), tCC= ∞
Input signals are stable
Operating Current
(Burst Mode)
IOL= 0Ma, Page Burst
ICC4
All Band Activated, tCCD = tCCD (min)
3
2
Refresh Current
ICC5
tRC ≥ tRC(min)
Self Refresh Current
ICC6
CKE ≤ 0.2V
Note: 1.Measured with outputs open. Addresses are changed only one time during tCC(min).
2.Refresh period is 32ms. Addresses are changed only one time during tCC(min).
Version
-7
100
2
2
25
10
10
10
25
10
120
120
120
1
Unit Note
mA 1
mA
mA
mA
mA
mA
mA
mA 1
mA 2
mA
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.1
4/29