EN27LN2G08 Datasheet, PDF (51/56 Pages) Eon Silicon Solution Inc. – 2 Gigabit (256M x 8), 3.3 V NAND Flash Memory

R_P vs t_RHOH vs C_L
EN27LN2G08
R_P value guidance
where I_L is the sum of the input currents of all devices tied to the R/ B# pin.
R_P (max) is determined by maximum permissible limit of tr
Data Protection & Power-up sequence
The timing sequence shown in the following figure is necessary for the power-on/off sequence.
The device internal initialization starts after the power supply reaches an appropriate level in the power
on sequence. During the initialization the device R/B# signal indicates the Busy state as shown in the
following figure. In this time period, the acceptable commands are 70h.
The WP# signal is useful for protecting against data corruption at power on/off.
AC Waveforms for Power Transition
This Data Sheet may be revised by subsequent versions
51
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. D, Issue Date: 2013/12/13