EN27LN2G08 Datasheet, PDF (39/56 Pages) Eon Silicon Solution Inc. – 2 Gigabit (256M x 8), 3.3 V NAND Flash Memory

EN27LN2G08
Block Erase
The block-based Erase operation is initiated by an Erase Setup command (60h), followed by a three-
cycle row address, in which only Plane address and Block address are valid while Page address is
ignored. The Erase Confirm command (D0h) following the row address starts the internal erasing
process. The two-step command sequence is designed to prevent memory content from being
inadvertently changed by external noise.
At the rising edge of WE# after the Erase Confirm command input, the internal control logic handles
erase and erase-verify. When the erase operation is completed, the host controller can check Status bit
(I/O0) to see if the erase operation is successfully done. The following figure illustrates a block erase
sequence, and the address input (the first page address of the selected block) is placed in between
commands 60h and D0h. After t_BERASE erase time, the R/B# de-asserts to ready state. Read Status
command (70h) can be issued right after D0h to check the execution status of erase operation.
Block Erase Operation
One-Time Programmable (OTP) Operations
This Eon flash device offers one-time programmable memory area. Thirty full pages of OTP data are
available on the device, and the entire range is guaranteed to be good. The OTP area is accessible only
through the OTP commands.
The OTP area leaves the factory in an unwritten state. The OTP area cannot be erased, whether it is
protected or not. Protecting the OTP area prevents further programming of that area.
The OTP area is only accessible while in OTP operation mode. To set the device to OTP operation
mode, issue the Set Feature (EFh-90h-01h) command. When the device is in OTP operation mode,
subsequent Read and/or Page Program are applied to the OTP area. When you want to come back to
normal operation, you need to use EFh-90h-00h for OTP mode release. Otherwise, device will
stay in OTP mode.
To program an OTP page, issue the Serial Data Input (80h) command followed by 5 address cycles.
The first two address cycles are column address that must be set as 00h. For the third cycle, select a
page in the range of 00h through 1Dh. The fourth and fifth cycle is fixed at 00h. Next, up to 2,112 bytes
of data can be loaded into data register. The bytes other than those to be programmed do not need to
be loaded. Random Data Input (85h) command in this device is prohibited. The Page Program confirms
(10h) command initiates the programming process. The internal control logic automatically executes the
programming algorithm, timing and verification. Please note that no partial-page program is allowed in
the OTP area. In addition, the OTP pages must be programmed in the ascending order. A programmed
OTP page will be automatically protected.
Similarly, to read data from an OTP page, set the device to OTP operation mode and then issue the
Read (00h-30h) command. The first two address cycles are column address that must be set as 00h
and Random Data Output (05h-E0h) command is prohibited as well.
This Data Sheet may be revised by subsequent versions
39
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. D, Issue Date: 2013/12/13