EN27LN2G08 Datasheet, PDF (45/56 Pages) Eon Silicon Solution Inc. – 2 Gigabit (256M x 8), 3.3 V NAND Flash Memory

EN27LN2G08
Two-Plane Cache Read
Two-Plane Cache Read is an extension of Cache Read, for a single plane with 2,112 byte data registers.
Since the device is equipped with two memory planes, the two sets of 2,112 byte data registers enables
a cache read of two pages. Two-Plane Cache Read is initiated by repeating command 60h followed by
three address cycles twice. In this case only same page of same block can be selected from each plane.
After Read Confirm command (33h) the 4,224 bytes of data within the selected two page are transferred
to the cache registers via data registers in less than 25us (t_R). After issuing Cache Read command
(31h), read data in the data registers is transferred to cache registers for a short period of time (t_DBSY).
Once the data is loaded into the cache registers from data registers, the data output of first plane can be
read out by issuing command 00h with five address cycles, command 05h with two column address and
finally E0h. The data output of second plane can be read out using the identical command sequences.
This Data Sheet may be revised by subsequent versions
45
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. D, Issue Date: 2013/12/13