EN27LN2G08 Datasheet, PDF (50/56 Pages) Eon Silicon Solution Inc. – 2 Gigabit (256M x 8), 3.3 V NAND Flash Memory

EN27LN2G08
Two-Plane Block Erase
Basic concept of Two-Plane Block Erase operation is identical to that of Two-Plane Page Program. Up
to two blocks, one from each plane can be simultaneously erased. Standard Block Erase command
sequences (Block Erase Setup command 60h followed by three address cycles) may be repeated up to
twice for erasing up to two blocks. Only one block should be selected from each plane. The Erase
Confirm command (D0h) initiates the actual erasing process. The completion is detected by monitoring
R/B pin or Ready/Busy status bit (I/O 6).
READY/BUSY#
The device has an R/B# output that provides a hardware method of indicating the completion of a page
program, erase and random read completion. The R/B# pin is normally high but transition to low after
program or erase command is written to the command register or random read is started after address
loading. It returns to high when the internal controller has finished the operation. The pin is an open-
drain driver thereby allowing two or more R/B# outputs to be Or-tied. Because pull-up resistor value is
related to tr (R/B#) and current drain during busy (ibusy), an appropriate value can be obtained with the
following reference chart (the following figure). Its value can be determined by the following guidance.
Read / Busy Pin Electrical Specifications
This Data Sheet may be revised by subsequent versions
50
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. D, Issue Date: 2013/12/13