EN27LN51208 Datasheet, PDF (40/46 Pages) Eon Silicon Solution Inc. – 512 Megabit (64 M x 8) SLC, 3.3 V NAND Flash Memory

Table 6. ID Definition Table
ID Access command = 90h
st
1 Cycle
nd
2 Cycle
(Maker Code) (Device Code)
C8h
D0h
3^rd Cycle
90h
4^th Cycle
95h
EN27LN51208
5^th Cycle
30h
11.9 Reset
The device offers a reset feature, executed by writing FFh to the command register. When the device is
in Busy state during random read, program or erase mode, the reset operation will abort these
operations. The contents of memory cells being altered are no longer valid, as the data will be partially
programmed or erased. The command register is cleared to wait for the next command, and the Status
Register is cleared to value C0h when WP# is high. If the device is already in reset state a new reset
command will be accepted by the command register. The R/B# pin changes to low for tRST after the
Reset command is written. Refer to Figure 32 below.
Figure 32. Reset Operation
Table 7. Device Status
Operation mode
After Power-up
00h Command is latched
After Reset
Waiting for next command
11.10 Cache Read
Cache Read is an extension of Page Read, and is available only within a block. The normal Page Read
command (00h-30h) is always issued before invoking Cache Read. After issuing the Cache Read
command (31h), read data of the designated page (page N) are transferred from data registers to cache
registers in a short time period of tDCBSYR, and then data of the next page (page N+1) is transferred to
data registers while the data in the cache registers are being read out. Host controller can retrieve
continuous data and achieve fast read performance by iterating Cache Read operation. The Read Start
for Last Page Cache Read command (3Fh) is used to complete data transfer from memory cells to data
registers.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2013/09/30