EN27LN51208 Datasheet, PDF (32/46 Pages) Eon Silicon Solution Inc. – 512 Megabit (64 M x 8) SLC, 3.3 V NAND Flash Memory

11. Device Operation
EN27LN51208
11.1 Page Read
Upon initial device power up, the device defaults to Read mode. This operation is also initiated by
writing 00h command, five-cycle address, and 30h command. After initial power up, the 00h command
can be skipped because it has been latched in the command register. The 2,112Byte of data on a page
are transferred to cache registers via data registers within 25us (t ). Host controller can detect the
R
completion of this data transfer by checking the R/B# output. Once data in the selected page have been
loaded into cache registers, each Byte can be read out in 45ns/ 25ns cycle time by continuously pulsing
RE#. The repetitive high-to-low transitions of RE# clock signal make the device output data starting from
the designated column address to the last column address.
The device can output data at a random column address instead of sequential column address by using
the Random Data Output command. Random Data Output command can be executed multiple times in
a page.
After power up, device is in read mode so 00h command cycle is not necessary to start a read operation.
A page read sequence is illustrated in Figure 23, where column address, page address are placed in
between commands 00h and 30h. After t read time, the R/B# de-asserts to ready state. Read Status
R
command (70h) can be issued right after 30h. Host controller can toggle RE# to access data starting
with the designated column address and their successive bytes.
Figure 23. Read Operation
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2013/09/30