EN27LN51208 Datasheet, PDF (19/46 Pages) Eon Silicon Solution Inc. – 512 Megabit (64 M x 8) SLC, 3.3 V NAND Flash Memory

8.4 Addressing for Program Operation
EN27LN51208
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of
the block to MSB (most significant bit) pages of the block. Random page address programming is
prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed.
Therefore, LSB page doesn’t need to be page 0.
8.5 System Interface Using CE# Don’t Care
For an easier system interface, CE# may be inactive during the data-loading or serial access as shown
below. The internal 2,112byte data registers are utilized as separate buffers for this operation and the
system design gets more flexible. In addition, for voice or audio applications that use slow cycle time on
the order of μ-seconds, de-activating CE# during the data-loading and serial access would provide
significant savings in power consumption.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2013/09/30