BCM43143KMLGT Datasheet, PDF (8/58 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio with USB/SDIO Host Interface

BCM43143 Advance Data Sheet
List of Figures
List of Figures
Figure 1: BCM43143 High-Level Block Diagram ............................................................................................... 2
Figure 2: BCM43143 System Diagram Showing Two Antennas and a Single Stream .................................... 10
Figure 3: BCM43143 Functional Block Diagram .............................................................................................. 11
Figure 4: Power Topology with the VDD33 (3.3V) Main Supply ...................................................................... 13
Figure 5: Recommended Oscillator Configuration ........................................................................................... 15
Figure 6: WLAN USB 2.0 Host Interface Block Diagram ................................................................................. 16
Figure 7: Enhanced MAC Block Diagram ........................................................................................................ 20
Figure 8: PHY Block Diagram .......................................................................................................................... 21
Figure 9: BCM43143 56-Pin QFN Package ..................................................................................................... 23
Figure 10: Power-Up Sequence Timing—3V Supply ...................................................................................... 44
Figure 11: Power-Up Sequence Timing—5V Supply with External DC-DC Conversion ................................. 45
Figure 12: Serial Flash Timing Diagram (STMicroelectronics-Compatible) ..................................................... 46
Figure 13: I²S Slave Mode Timing ................................................................................................................... 47
Figure 14: SDIO Bus Timing (Default Mode) ................................................................................................... 49
Figure 15: SDIO Bus Timing (High-Speed Mode)............................................................................................ 50
Figure 16: 7 mm × 7 mm, 56-pin QFN package............................................................................................... 55
Broadcom^®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
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