BCM43143KMLGT Datasheet, PDF (48/58 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio with USB/SDIO Host Interface

BCM43143 Advance Data Sheet
I²S Slave Mode Tx Timing
I²S Slave Mode Tx Timing
In I²S slave mode, the serial clock (I2S_BITCLK) input speed can vary up to a maximum of 12.288 MHz.
I²S Slave mode timing is illustrated in Figure 13.
Figure 13: I²S Slave Mode Timing
BITCLK
WS
SD
BITCLK
SD/WS
MSB
WORD n – 1
Right Channel
T
t _RC
thtr _{= 0}
t _{dtr = 0.8T}
WORD n
Left Channel
t _{LC = 0.35T}
T = clock period
Ttr = minimum allowed clock period for transmitter
T > Ttr
LSB
t _{HC = 0.35T}
MSB
WORD n + 1
Right Channel
V _{H = 2.0V}
V _{L = 0.8V}
Parameter
Clock period T
Slave Mode:
Clock accepted by
transmitter or receiver:
HIGH t_HC
LOW t_LC
rise time t_RC
Table 20: Timing for I²S Transmitters and Receivers
Transmitter
Lower Limit
Upper Limit
Min
T_tr
Max
Min
Max
Receiver
Lower Limit
Min
T_tr
Max
0.35 T_r
0.35 T_r
0.15 T_tr
0.35 T_r
0.35 T_r
Broadcom^®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 47