BCM43143KMLGT Datasheet, PDF (46/58 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio with USB/SDIO Host Interface

BCM43143 Advance Data Sheet
Power Sequence Timing
Figure 11: Power-Up Sequence Timing—5V Supply with External DC-DC Conversion
t₁
t₂
t₃
SR_VDDBAT5V
WRF_PA(D)_VDD3P3
USB_AVDD3P3
VDDIO
SR_VLX
VDDC
internal reset
interface
43143 TRI-STATE
Table 18: Power-Up Timing Parameters
Symbol Description
Minimum Typical Maximum Unit
t₁
SR_VDDBAT5V to 3P3 active
0^a
50^b
–
µs
t₂
Time from VDDIO rising edge to VDDC reaching –
–
850
µs
1.2V
t₃
Time from VDDC reaching 1.2V to internal reset 30
35
50
ms
deactivation
a. In the case of the 3.3V power supply, t1 = 0 for SR_VDDBAT5V, WRF_PA_VDD3P3, and WRF_PAD_VDD3P3.
b. In the case of the 5V power supply, SR_VDD_BAT5V is directly connected to 5V, but the connection to
WRF_PA_VDD3P3, WRF_PAD_VDD3P3, and VDDIO must be made through a DC-DC converter chip to
convert 5V to 3V3. Since the converter chip introduces a delay in the ramp-up time, t1 = 50 µs (nominal). The
actual value of t1 will vary slightly based on the particular DC-DC converter chip used in the design.
Broadcom^®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 45