BCM43143KMLGT Datasheet, PDF (45/58 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio with USB/SDIO Host Interface

BCM43143 Advance Data Sheet
Timing Characteristics
Section 13: Timing Characteristics
Power Sequence Timing
The recommended power-up sequence is to bring up the power supplies in the order of the rated voltage. This
power-up sequence minimizes the possibility of a latchup condition.
In the case of a 3.3V supply (see Figure 10), the 3.3V supplied to SR_VDDBAT5V, WRF_PA_VDD3P3,
WRF_PAD_VDD3P3, USB_AVDD3P3, and VDDIO can ramp at the same time.
In the case of a 5V supply (see Figure 11 on page 45), the 5V first ramps on SR_VDDBAT5V, followed by bring-
up of the 3.3V supply to WRF_PA_VDD3P3, WRF_PAD_VDD3P3, USB_AVDD3P3, and VDDIO. The power-
up timing parameters for both configurations are shown in Table 18 on page 45.
Figure 10: Power-Up Sequence Timing—3V Supply
SR_VDDBAT5V
t₂
t₃
WRF_PA(D)_VDD3P3
USB_AVDD3P3
VDDIO
SR_VLX
VDDC
Internal Reset
Interface
BCM43143 TRI-STATE
Broadcom^®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 44