BCM43143KMLGT Datasheet, PDF (13/58 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio with USB/SDIO Host Interface

BCM43143 Advance Data Sheet
Power Management and Resets
Section 2: Power Management and Resets
Power Management
The BCM43143 includes an internal Power Management Unit (PMU). The PMU takes care of powering up the
chip, and also enables and disables clocks based on clock requests sent from BCM43143 internal blocks.
Power Topology
The BCM43143 contains a high-efficiency power topology to convert input supply voltages to the supply
voltages required by the device’s internal blocks. A CBUCK switching regulator is used to convert the input
supply to 1.35V. Internal LDOs perform a low-noise conversion from 1.35V to 1.2V. As shown in Figure 4 on
page 13, the BCM43143 supports two power supply configurations:
• A 3.3V power supply, connected to SR_VDDBAT5V, WRF_PA_VDD3P3, and WRF_PAD_VDD3P3.
• A 5V power supply connected to SR_VDDBAT5V, WRF_PA_VDD3P3, and WRF_PAD_VDD3P3
connected to 3.3V. The latter can be obtained through a DC-DC conversion as shown in Figure 4 on page
13.
The default VDDIO supply of the BCM43143 is 3.3V. In SDIO mode, the BCM43143 supports an SDIO interface
specific voltage range of 1.8V to 3.3V. Refer to pin 46 description in Table 4 on page 26. All VDDIO pins other
than pin 46 remain at 3.3V as described in Table 4 on page 26.
Broadcom^®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 12