BCM43143KMLGT Datasheet, PDF (52/58 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio with USB/SDIO Host Interface

BCM43143 Advance Data Sheet
SDIO High Speed Mode Timing
Table 22: SDIO Bus Timing^a Parameters (High-Speed Mode)
Parameter
Symbol Minimum Typical
SDIO CLK (all values are referred to minimum VIH and maximum VIL^b)
Frequency – data transfer mode
fPP
0
–
Frequency – identification mode
fOD
0
–
Clock low time
Clock high time
tWL
7
–
tWH
7
–
Clock rise time
tTLH
–
–
Clock low time
tTHL
–
–
Inputs: CMD, DAT (referenced to CLK)
Input setup time
tISU
6
–
Input hold time
tIH
2
–
Outputs: CMD, DAT (referenced to CLK)
Output delay time – data transfer mode
tODLY –
–
Output hold time
Total system capacitance (each line)
tOH
2.5
–
CL
–
–
a. Timing is based on CL ≤40 pF load on CMD and data.
b. min(Vih) = 0.7 × VDDIO_SD and max(Vil) = 0.2 × VDDIO_SD.
c. 0 - 46 MHz when running at 1.8V.
Maximum Unit
50^c
MHz
400
kHz
–
ns
–
ns
3
ns
3
ns
–
ns
–
ns
14
ns
–
ns
40
pF
Broadcom^®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 51