BCM43143KMLGT Datasheet, PDF (21/58 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio with USB/SDIO Host Interface

BCM43143 Advance Data Sheet
IEEE 802.11n MAC Description
Figure 7: Enhanced MAC Block Diagram
Host Interface (Host Registers)
TX Status FIFO
Power
Management
Timing and
Control
Six TX FIFOs
Templates
RX FIFO
Wireless Security Engine
TX Engine
RX Engine
PHY Interface
Code Memory
Programmable
State Machine
(PSM)
Data Memory
The host interface consists of registers for controlling and monitoring the status of the MAC core and interfacing
with the TX/RX FIFOs. For transmission, 32 KB of FIFO buffering is available that can be dynamically allocated
to six transmit queues plus template space for beacons, ACKs, and probe responses. Whenever the host has
a frame to transmit, the host queues the frame into one of the transmit FIFOs with a TX descriptor containing
TX control information. The PSM schedules the transmission on the medium depending on the frame type,
transmission rules in the IEEE 802.11™ protocol, and the current medium occupancy scenario. After the
transmission completes, a TX status is returned to the host, informing the host of the transmission.
The MAC contains a 10 KB RX FIFO. Received frames are sent to the host along with RX descriptors that
contain additional frame reception information.
The power management block maintains power management state information of the core (and of the
associated STAs in the case of an AP) to help with dynamic frame transmission decisions by the core.
The wireless security engine performs the required encryption/decryption on the TX/RX frames. This block
supports separate transmit and receive keys with four shared keys and 50 link-specific keys. The link-specific
keys are used to establish a secure link between any two network nodes. The wireless security engine supports
the following encryption schemes that can be selected on a per-destination basis:
• None: The wireless security engine acts as a pass-through
• WEP: 40-bit secure key and 24-bit IV as defined in IEEE Std. 802.11-2007
• WEP128: 104-bit secure key and 24-bit IV
• TKIP: IEEE Std. 802.11-2007
• AES: IEEE Std. 802.11-2007
The transmit engine is responsible for the byte flow from the TX FIFO to the PHY interface through the
encryption engine and the addition of a CRC-32 Frame Check Sequence (FCS) as required by IEEE 802.11-
2007. Similarly, the receive engine is responsible for byte flow from the PHY interface to the RX FIFO through
the decryption engine and for detection of errors in the RX frame.
The timing block performs the TSF, NAV, and IFS functionality as described in IEEE Std. 802.11-2007.
The Programmable State Machine (PSM) coordinates the operation of different hardware blocks required for
both transmission and reception. The PSM also maintains the statistics counters required for MIB support.
Broadcom^®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
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