BCM43143KMLGT Datasheet, PDF (31/58 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio with USB/SDIO Host Interface

BCM43143 Advance Data Sheet
Strapping Options
Strapping Options
The pins listed in Table 5 are sampled at Power-On Reset (POR) to determine the various operating modes.
Sampling occurs within a few milliseconds following internal POR or deassertion of external POR. After POR,
each pin assumes the function specified in the signal descriptions table. Each pin has an internal pull-up (PU)
or pull-down (PD) resistor that determines the default mode. To change the mode, connect an external PU
resistor to VDDIO or a PD resistor to GND (use 10 kΩ or less)¹.
Table 5: Strapping Options
Signal Name Mode
Default Description
[UART_RX,
UART_TX]
RemapToROM[1:0]
[PD,PU]
00 = Boot from SRAM, ARMCM3 in reset, no SFLASH
connected
01 = Boot from ROM, no SFLASH connected (default)
10 = Boot from SFLASH
11 = Invalid
GPIO17
SDIOEnabled
PD
0 = USB Enabled, SDIO pins can be GPIO or I²S (default)
1 = SDIO Enabled
GPIO18
SDIOIso
PD
0 = SDIO pads are not in Isolation mode (default)
1 = Keep SDIO pads in Isolation mode
SFLASH_SI SDIOHighDrive
PD
0 = SDIO pins drive strength set by SDIOd core or PMU Chip
Control (= default)
1 = SDIO pins drive strength set by SDIOd core to either 12 mA
or 16 mA
1. BCM43143 reference board schematics can be obtained through your Broadcom representative.
Broadcom^®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
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