BCM43143KMLGT Datasheet, PDF (50/58 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio with USB/SDIO Host Interface

BCM43143 Advance Data Sheet
SDIO Default Mode Timing
SDIO Default Mode Timing
SDIO default mode timing is shown by the combination of Figure 14 and Table 21.
Figure 14: SDIO Bus Timing (Default Mode)
f_PP
t_WL
t_WH
SDIO_CLK
Input
t_THL
t_TLH
t_ISU
t_IH
Output
t_ODLY
(max)
t_ODLY
(min)
Table 21: SDIO Bus Timing^a Parameters (Default Mode)
Parameter
Symbol Minimum Typical
SDIO CLK (All values are referred to minimum VIH and maximum VIL^b)
Frequency – data transfer mode
Frequency – identification mode
Clock low time
Clock high time
Clock rise time
Clock low time
fPP
0
–
fOD
0
–
tWL
10
–
tWH
10
–
tTLH
–
–
tTHL
–
–
Inputs: CMD, DAT (referenced to CLK)
Input setup time
Input hold time
tISU
5
–
tIH
5
–
Outputs: CMD, DAT (referenced to CLK)
Output delay time – data transfer mode
tODLY 0
–
Output delay time – identification mode
tODLY 0
–
a. Timing is based on CL ≤40 pF load on CMD and data.
b. min(Vih) = 0.7 × VDDIO_SD and max(Vil) = 0.2 × VDDIO_SD.
Maximum Unit
25
MHz
400
kHz
–
ns
–
ns
10
ns
10
ns
–
ns
–
ns
14
ns
50
ns
Broadcom^®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 49