BCM43143KMLGT Datasheet, PDF (15/58 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio with USB/SDIO Host Interface

BCM43143 Advance Data Sheet
WLAN Global Functions
Section 3: WLAN Global Functions
GPIO Interface
There are 19 General-Purpose I/O (GPIO) pins provided on the BCM43143. GPIOs 0–18 are multiplexed with
the JTAG, SDIO, I²S, SFlash, and Serial Enhanced Coexistence Interface (SECI) functions. These pins can be
used to interface to various external devices. Upon power-up and reset, these pins become tristated.
Subsequently, they can be programmed to be either input or output pins via the GPIO control register. A
programmable internal pull-up/pull-down resistor is included on each GPIO. If a GPIO output enable is not
asserted, and the corresponding GPIO signal is not being driven externally, the GPIO state is determined by its
programmable resistor.
OTP
The BCM43143 has 2 Kbits of on-chip One-Time Programmable (OTP) memory that can be used for non-
volatile storage of WLAN information such as a MAC address and other hardware-specific board and interface
configuration parameters.
JTAG Interface
The BCM43143 supports the IEEE 1149.1 JTAG boundary-scan standard for testing a packaged device on a
manufactured board. The JTAG interface is enabled by driving the JTAG_SEL pin high.
Broadcom^®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 14