BCM43143KMLGT Datasheet, PDF (17/58 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio with USB/SDIO Host Interface

BCM43143 Advance Data Sheet
WLAN USB 2.0 Host Interface
Section 4: WLAN USB 2.0 Host Interface
The BCM43143 USB interface can be set to operate as a USB 2.0 port. Features include the following:
• A USB 2.0 protocol engine that supports the following:
– A Parallel Interface Engine (PIE) between packet buffers and USB transceiver
– Up to nine endpoints, including Configurable Control Endpoint 0
• Separate endpoint packet buffers with a 512-byte FIFO buffer each
• Host-to-device communication for bulk, control, and interrupt transfers
• Configuration and status registers
Figure 6 shows the blocks in the device core.
Figure 6: WLAN USB 2.0 Host Interface Block Diagram
32-Bit On-Chip Communication System
RX FIFO
DMA Engines
TX FIFOs
Endpoint Management Unit
USB 2.0 Protocol Engine
USB 2.0 PHY
D+
D-
The USB 2.0 PHY handles the USB protocol and the serial signaling interface between the host and device. It
is primarily responsible for data transmission and recovery. On the transmit side, data is encoded, along with a
clock, using the NRZI scheme with bit stuffing to ensure that the receiver detects a transition in the data stream.
A SYNC field that precedes each packet enables the receiver to synchronize the data and clock recovery
circuits. On the receive side, the serial data is deserialized, unstuffed, and checked for errors. The recovered
data and clock are then shifted to the clock domain that is compatible with the internal bus logic.
The endpoint management unit contains the PIE control logic and the endpoint logic. The PIE interfaces
between the packet buffers and the USB transceiver. It handles packet identification (PID), USB packets, and
transactions.
Broadcom^®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
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