BCM43143KMLGT Datasheet, PDF (18/58 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio with USB/SDIO Host Interface

BCM43143 Advance Data Sheet
Link Power Management (LPM) Support
The endpoint logic contains nine uniquely addressable endpoints. These endpoints are the source or sink of
communication flow between the host and the device. Endpoint zero is used as a default control port for both
the input and output directions. The USB system software uses this default control method to initialize and
configure the device information and allows USB status and control access. Endpoint zero is always accessible
after a device is attached, powered, and reset.
Endpoints are supported by 512-byte FIFO buffers, one for each IN endpoint and one shared by all OUT
endpoints. Both TX and RX data transfers support a DMA burst of 4, which guarantees low latency and
maximum throughput performance. The RX FIFO can never overflow by design. The maximum USB packet size
cannot be more than 512 bytes.
Link Power Management (LPM) Support
The USB 2.0 host interface supports a power management feature called Link Power Management (LPM) which
is similar to the existing suspend/resume, but has transitional latencies of tens of microseconds between power
states (instead of three to greater than 20 millisecond latencies of the USB 2.0 suspend/resume). LPM simply
adds a new feature and bus state that co-exists with the USB 2.0 defined suspend/resume.
I²S Interface
The I²S interface for audio supports slave mode transmit 2.1 or 5.1 channel operation. The I²S signals are:
• I²S bit clock: I2S_BITCLK
• I²S Word Select: I2S_WS
• I²S Data Out: I2S_SDOUT
I2S_BITCLK and I2S_WS are inputs, while I2S_SDOUT is an output. Channel word lengths of 16 bits, 20 bits,
24 bits, and 32 bits are supported, and the data is justified so that the MSB of the left-channel data is aligned
with the MSB of the I²S bus, per the I²S specification. The MSB of each data word is transmitted one bit clock
cycle after the I2S_WS transition, synchronous with the falling edge of bit clock. Left-channel data is transmitted
when I2S_WS is low, and right-channel data is transmitted when I2S_WS is high. An embedded 128 x 32 bits
single port SRAM for data processing enhances the performance of the interface.
The bit depth of I²S is 16, 20, 24, and 32.
Variable sampling rates are also supported:
• 8k, 12k, 16k, 24k, 32k, 48k, 96k with a 12.288 MHz master clock used by the external master receiver and/
or controller
• 22.05k, 44.1k, 88.2k with a 11.2896 MHz master clock used by the external master receiver and/or
controller
• 96k with a 24.567 MHz master clock used by the external master receiver and/or controller
The BCM43143 needs an external clock source input on the slave clock pin for the I²S interface. The slave clock
frequency is dependent upon the audio sample rate and the external I²S codec.
Broadcom^®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
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