SAM9260_14 Datasheet, PDF (88/784 Pages) ATMEL Corporation – AT91SAM ARM-based Embbedded MPU

Before performing the jump to the application in internal SRAM, all the PIOs and peripherals used in the boot pro-
gram are set to their reset state.
Table 13-11. Pins Driven during Boot Program Execution
Peripheral
Pin
SPI0
MOSI
SPI0
MISO
SPI0
SPCK
SPI0
NPCS0
SPI0
NPCS1
PIOC
NANDCS
DBGU
DRXD
DBGU
DTXD
PIO Line
PIOA1
PIOA0
PIOA2
PIOA3
PIOC11
PIOC14
PIOB14
PIOB15
13.8 ROM Code Change Log
Here are the evolutions between ROM Code V1.4 and V1.7:
• User Reset is no longer enabled
• NAND Flash Ready/Busy pin (PIOC 13) is no longer used
• There are no more Timeouts in the NAND Flash Boot sequence
Note: To know which ROM Code version is in the chip, use the SAM-BA Monitor command “V#” (see Table 13-8 on page 86)
SAM9260 [DATASHEET] 88
6221K–ATARM–15-Oct-12