SAM9260_14 Datasheet, PDF (143/784 Pages) ATMEL Corporation – AT91SAM ARM-based Embbedded MPU

19.7.2 32-bit SDRAM
19.7.2.1 Hardware Configuration
D[0..31]
A[0..14]
(Not used A12)
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A13 ^SDA10
BA0
BA1
A14
SDCKE
SDCK
A0
CFIOR_NBS1_NWR1
CAS
RAS
SDWE
SDCS_NCS1
SDA10
BA0
BA1
SDCKE
SDCK
1%6
1%6
CAS
RAS
SDWE
U1
23
24
25
26
29
30
31
32
33
34
22
35
20
21
36
40
37
38
15
39
17
18
16
19
A0
A1
MT48LC16M16A2
DQ0
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
DQ12
BA0
DQ13
BA1
DQ14
DQ15
A12
N.C
VDD
VDD
CKE
VDD
VDDQ
CLK
VDDQ
VDDQ
DQML
VDDQ
DQMH
VSS
CAS
VSS
RAS
VSS
VSSQ
VSSQ
WE
VSSQ
CS
VSSQ
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
1
14
27
3
9
43
49
28
41
54
6
12
46
52
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
3V3
256 Mbits
C1 100NF
C2 100NF
C3 100NF
C4 100NF
C5 100NF
C6 100NF
C7 100NF
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A13
A14
A1
CFIOW_NBS3_NWR3
TSOP54 PACKAGE
SDA10
BA0
BA1
SDCKE
SDCK
1%6
1%6
CAS
RAS
SDWE
U2
23
24
25
26
29
30
31
32
33
34
22
35
20
21
36
40
37
38
15
39
17
18
16
19
A0
A1
MT48LC16M16A2
DQ0
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
DQ12
BA0
DQ13
BA1
DQ14
DQ15
A12
N.C
VDD
VDD
CKE
VDD
VDDQ
CLK
VDDQ
VDDQ
DQML
VDDQ
DQMH
VSS
CAS
VSS
RAS
VSS
VSSQ
VSSQ
WE
VSSQ
CS
VSSQ
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
1
14
27
3
9
43
49
28
41
54
6
12
46
52
256 Mbits
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
3V3
C8 100NF
C9 100NF
C10 100NF
C11 100NF
C12 100NF
C13 100NF
C14 100NF
19.7.2.2 Software Configuration
The following configuration has to be performed:
• Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment
Register located in the bus matrix memory space.
• Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency.
The Data Bus Width is to be programmed to 32 bits. The data lines D[16..31] are multiplexed with PIO lines and
thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller.
The SDRAM initialization sequence is described in the “SDRAM device initialization” part of the SDRAM controller.
SAM9260 [DATASHEET]
6221K–ATARM–15-Oct-12
143