SAM9260_14 Datasheet, PDF (417/784 Pages) ATMEL Corporation – AT91SAM ARM-based Embbedded MPU

31.7.1 Baud Rate Generator
The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the
transmitter.
The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register
(US_MR) between:
• the Master Clock MCK
• a division of the Master Clock, the divider being product dependent, but generally set to 8
• the external clock, available on the SCK pin
The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate
Generator Register (US_BRGR). If CD is programmed at 0, the Baud Rate Generator does not generate any clock.
If CD is programmed at 1, the divider is bypassed and becomes inactive.
If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin
must be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least
4.5 times lower than MCK.
Figure 31-3. Baud Rate Generator
USCLKS
MCK
0
MCK/DIV
1
Reserved
SCK
2
3
CD
CD
16-bit Counter
>1
1
0
0
0
1
SYNC
USCLKS = 3
SCK
FIDI
OVER
Sampling
Divider
SYNC
0
Baud Rate
Clock
1
Sampling
Clock
31.7.1.1 Baud Rate in Asynchronous Mode
If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is
field programmed in the Baud Rate Generator Register (US_BRGR). The resulting clock is provided to the receiver
as a sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR.
If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sam-
pling is performed at 16 times the baud rate clock.
The following formula performs the calculation of the Baud Rate.
Baudrate = ₍--^S-₈----₍^e--₂-^l--^e--–--^c--_O-^t--^e--_v--^d--_e--^C-_r---₎^l--^oC----^c-_D--^k---₎
This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that
OVER is programmed at 1.
SAM9260 [DATASHEET]
6221K–ATARM–15-Oct-12
417