SAM9260_14 Datasheet, PDF (196/784 Pages) ATMEL Corporation – AT91SAM ARM-based Embbedded MPU

6. An All Banks Precharge command is issued to the SDRAM devices. The application must set Mode to 2 in
the Mode Register and perform a write access to any SDRAM address.
7. Eight auto-refresh (CBR) cycles are provided. The application must set the Mode to 4 in the Mode Regis-
ter and perform a write access to any SDRAM location eight times.
8. A Mode Register set (MRS) cycle is issued to program the parameters of the SDRAM devices, in particu-
lar CAS latency and burst length. The application must set Mode to 3 in the Mode Register and perform a
write access to the SDRAM. The write address must be chosen so that BA[1:0] are set to 0. For example,
with a 16-bit 128 MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access
should be done at the address 0x20000000.
9. For mobile SDRAM initialization, an Extended Mode Register set (EMRS) cycle is issued to program the
SDRAM parameters (TCSR, PASR, DS). The application must set Mode to 5 in the Mode Register and
perform a write access to the SDRAM. The write address must be chosen so that BA[1] or BA[0] are set to
1. For example, with a 16-bit 128 MB SDRAM, (12 rows, 9 columns, 4 banks) bank address the SDRAM
write access should be done at the address 0x20800000 or 0x20400000.
10. The application must go into Normal Mode, setting Mode to 0 in the Mode Register and performing a write
access at any location in the SDRAM.
11. Write the refresh rate into the count field in the SDRAMC Refresh Timer register. (Refresh rate = delay
between refresh cycles). The SDRAM device requires a refresh every 15.625 µs or 7.81 µs. With a 100
MHz frequency, the Refresh Timer Counter Register must be set with the value 1562(15.652 µs x 100
MHz) or 781(7.81 µs x 100 MHz).
After initialization, the SDRAM devices are fully functional.
Note: 1. It is strongly recommended to respect the instructions stated in Step 5 of the initialization process in order to be
certain that the subsequent commands issued by the SDRAMC will be taken into account.
Figure 21-1. SDRAM Device Initialization Sequence
SDCKE
t_RP
SDCK
t_RC
t_MRD
SDRAMC_A[9:0]
A10
SDRAMC_A[12:11]
SDCS
RAS
CAS
SDWE
NBS
Inputs Stable for
200 μsec
Precharge All Banks
1st Auto-refresh
8th Auto-refresh
MRS Command
Valid Command
SAM9260 [DATASHEET]
6221K–ATARM–15-Oct-12
196