SAM9260_14 Datasheet, PDF (195/784 Pages) ATMEL Corporation – AT91SAM ARM-based Embbedded MPU

21.3.1.2 16-bit Memory Data Bus Width
Table 21-5. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0]
Row[10:0]
Column[7:0]
M0
Bk[1:0]
Row[10:0]
Column[8:0]
M0
Bk[1:0]
Row[10:0]
Column[9:0]
M0
Bk[1:0]
Row[10:0]
Column[10:0]
M0
Table 21-6. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0]
Row[11:0]
Column[7:0]
M0
Bk[1:0]
Row[11:0]
Column[8:0]
M0
Bk[1:0]
Row[11:0]
Column[9:0]
M0
Bk[1:0]
Row[11:0]
Column[10:0]
M0
Table 21-7. SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0]
Row[12:0]
Column[7:0]
M0
Bk[1:0]
Row[12:0]
Column[8:0]
M0
Bk[1:0]
Row[12:0]
Column[9:0]
M0
Bk[1:0]
Row[12:0]
Column[10:0]
M0
Notes: 1. M0 is the byte address inside a 16-bit half-word.
2. Bk[1] = BA1, Bk[0] = BA0.
21.4 Product Dependencies
21.4.1 SDRAM Device Initialization
The initialization sequence is generated by software. The SDRAM devices are initialized by the following
sequence:
1. SDRAM features must be set in the configuration register: asynchronous timings (TRC, TRAS, etc.), num-
ber of columns, rows, CAS latency, and the data bus width.
2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive strength (DS) and partial array
self refresh (PASR) must be set in the Low Power Register.
3. The SDRAM memory type must be set in the Memory Device Register.
4. A minimum pause of 200 µs is provided to precede any signal toggle.
5. ⁽¹⁾A NOP command is issued to the SDRAM devices. The application must set Mode to 1 in the Mode
Register and perform a write access to any SDRAM address.
SAM9260 [DATASHEET]
6221K–ATARM–15-Oct-12
195