SAM9260_14 Datasheet, PDF (464/784 Pages) ATMEL Corporation – AT91SAM ARM-based Embbedded MPU

Figure 32-6. Transmitter Clock Management
TK (pin)
Receiver
Clock
MUX
Divider
Clock
CKS
Tri_state
Controller
CKO
Data Transfer
INV
MUX
Clock
Output
Tri-state
Controller
Transmitter
Clock
CKI
CKG
32.7.1.3 Receiver Clock Management
The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the
RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register).
Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR.
The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output
is configured by the SSC_RCMR register. The Receive Clock Inversion (CKI) bits have no effect on the clock out-
puts. Programming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive
Clock (CKO field) can lead to unpredictable results.
Figure 32-7. Receiver Clock Management
RK (pin)
Transmitter
Clock
MUX
Tri-state
Controller
Clock
Output
Divider
Clock
CKO
Data Transfer
CKS
INV
MUX
Tri-state
Controller
Receiver
Clock
CKI
CKG
32.7.1.4 Serial Clock Ratio Considerations
The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK
or RK pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock
speed allowed on the RK pin is:
– Master Clock divided by 2 if Receiver Frame Synchro is input
SAM9260 [DATASHEET]
6221K–ATARM–15-Oct-12
464