SAM9260_14 Datasheet, PDF (183/784 Pages) ATMEL Corporation – AT91SAM ARM-based Embbedded MPU

In page mode, the programming of the read timings is described in Table 20-7:
Table 20-7. Programming of Read Timings in Page Mode
Parameter
Value
Definition
READ_MODE
‘x’
No impact
NCS_RD_SETUP ‘x’
No impact
NCS_RD_PULSE t_pa
NRD_SETUP
‘x’
Access time of first access to the page
No impact
NRD_PULSE
t_sa
NRD_CYCLE
‘x’
Access time of subsequent accesses in the page
No impact
The SMC does not check the coherency of timings. It will always apply the NCS_RD_PULSE timings as page
access timing (t_pa) and the NRD_PULSE for accesses to the page (t_sa), even if the programmed value for t_pa is
shorter than the programmed value for t_sa.
20.13.2 Byte Access Type in Page Mode
The Byte Access Type configuration remains active in page mode. For 16-bit or 32-bit page mode devices that
require byte selection signals, configure the BAT field of the SMC_REGISTER to 0 (byte select access type).
20.13.3 Page Mode Restriction
The page mode is not compatible with the use of the NWAIT signal. Using the page mode and the NWAIT signal
may lead to unpredictable behavior.
20.13.4 Sequential and Non-sequential Accesses
If the chip select and the MSB of addresses as defined in Table 20-6 are identical, then the current access lies in
the same page as the previous one, and no page break occurs.
Using this information, all data within the same page, sequential or not sequential, are accessed with a minimum
access time (t_sa). Figure 20-35 illustrates access to an 8-bit memory device in page mode, with 8-byte pages.
Access to D1 causes a page access with a long access time (t_pa). Accesses to D3 and D7, though they are not
sequential accesses, only require a short access time (t_sa).
If the MSB of addresses are different, the SMC performs the access of a new page. In the same way, if the chip
select is different from the previous access, a page break occurs. If two sequential accesses are made to the page
mode memory, but separated by an other internal or external peripheral access, a page break occurs on the sec-
ond access because the chip select of the device was deasserted between both accesses.
SAM9260 [DATASHEET]
6221K–ATARM–15-Oct-12
183