SAM9260_14 Datasheet, PDF (252/784 Pages) ATMEL Corporation – AT91SAM ARM-based Embbedded MPU

25.8 Clock Switching Details
25.8.1 Master Clock Switching Timings
Table 25-1 and Table 25-2 give the worst case timings required for the Master Clock to switch from one selected
clock to another one. This is in the event that the prescaler is deactivated. When the prescaler is activated, an addi-
tional time of 64 clock cycles of the new selected clock has to be added.
Table 25-1. Clock Switching Timings (Worst Case)
From
Main Clock
SLCK
To
Main Clock
–
4 x SLCK +
2.5 x Main Clock
SLCK
PLL Clock
0.5 x Main Clock +
4.5 x SLCK
0.5 x Main Clock +
4 x SLCK +
PLLCOUNT x SLCK +
2.5 x PLLx Clock
–
2.5 x PLL Clock +
5 x SLCK +
PLLCOUNT x SLCK
PLL Clock
3 x PLL Clock +
4 x SLCK +
1 x Main Clock
3 x PLL Clock +
5 x SLCK
2.5 x PLL Clock +
4 x SLCK +
PLLCOUNT x SLCK
Notes: 1. PLL designates either the PLL A or the PLL B Clock.
2. PLLCOUNT designates either PLLACOUNT or PLLBCOUNT.
Table 25-2. Clock Switching Timings Between Two PLLs (Worst Case)
From
PLLA Clock
PLLB Clock
To
PLLA Clock
2.5 x PLLA Clock +
4 x SLCK +
PLLACOUNT x SLCK
3 x PLLA Clock +
4 x SLCK +
1.5 x PLLA Clock
PLLB Clock
3 x PLLB Clock +
4 x SLCK +
1.5 x PLLB Clock
2.5 x PLLB Clock +
4 x SLCK +
PLLBCOUNT x SLCK
SAM9260 [DATASHEET]
6221K–ATARM–15-Oct-12
252