405EX Datasheet, PDF (63/67 Pages) Applied Micro Circuits Corporation – PowerPC 405EX Embedded Processor

PPC405EX – PowerPC 405EX Embedded Processor
Revision 1.09 - August 21, 2007
Preliminary Data Sheet
Table 24. I/O Timing—DDR SDRAM Read Timing T_SD and T_HD
1. T_SD and T_HD are measured under worst case conditions.
2. Clock speed for the values in the table is 200MHz.
3. The time values in the table include 1/4 of a cycle at 200MHz (5ns x 0.25 = 1.25 ns).
4. To obtain adjusted T_SD and T_HD values for lower clock frequencies, subtract 0.75 ns from the values in the table and add 1/4
of the cycle time for the lower clock frequency (e.g., T_SD - 1.25 + 0.25T_CYC).
Signal Names
MemData00:07
MemData08:15
MemData16:23
MemData24:31
ECC0:7
Reference Signal
DQS0
DQS1
DQS2
DQS3
DQS4
Read Data vs DQS Set up
T_SD (ns)
0.35
0.35
0.35
0.35
0.35
Read Data vs DQS Hold
T_HD (ns)
0.45
0.45
0.45
0.45
0.45
In the following example, the data strobes (DQS) and the data are shown to be coincident. There is actually a slight
skew as specified by the SDRAM specifications, and there can be additional skew due to loading and signal
routing. It is recommended that the signal length for all of the DQS signals be matched.
The following example shows the timing relationship between SDRAM DDR Data at the input pin and storing the
data in Stage 1.
AMCC Proprietary
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