405EX Datasheet, PDF (40/67 Pages) Applied Micro Circuits Corporation – PowerPC 405EX Embedded Processor

PPC405EX – PowerPC 405EX Embedded Processor
Revision 1.09 - August 21, 2007
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 3 of 7)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Description
I/O
Type
System Interface
SysClk
System input clock.
3.3V tolerant
I
2.5V CMOS
receiver
SysErr
Machine check exception has occurred.
O
3.3V tolerant
2.5V CMOS
SysReset
TestEn
Main system reset. This signal may be driven by the PPC405EX to
cause a board level reset to occur.
Test enable. Reserved for manufacturing LSSD test.
I/O
3.3V tolerant
2.5V CMOS
3.3V LVTTL
I
receiver
w/pull-down
Halt
External request to stop the processor.
3.3V LVTTL
I
receiver
w/pull-up
TmrClk
GPIO00:27
GPIO29:31
Processor timer external input.
I
General purpose I/O. Most of the GPIO signals are multiplexed with
other signals. Which signal is connected to the external pin depends I/O
on the setting of bits in the GPIO registers.
3.3V LVTTL
receiver
w/pull-up
3.3V LVTTL
GPIO28
General purpose I/O. Most of the GPIO signals are multiplexed with
other signals. Which signal is connected to the external pin depends
on the setting of bits in the GPIO registers.
I/O
3.3V tolerant
2.5V CMOS
PSROUser
Performance screen ring output. Use for module characterization and
screening only.
O
Trace Interface
TrcClk
Trace interface clock. Operates at half the CPU core frequency.
O
3.3V LVTTL
TS0E
TS1E
Even trace execution status.
I/O 3.3V LVTTL
TS0O
TS1O
Odd trace execution status.
I/O 3.3V LVTTL
TS0:3
Trace status.
I/O 3.3V LVTTL
Notes
1
1, 2
3
3
40
AMCC Proprietary