405EX Datasheet, PDF (60/67 Pages) Applied Micro Circuits Corporation – PowerPC 405EX Embedded Processor

PPC405EX – PowerPC 405EX Embedded Processor
Revision 1.09 - August 21, 2007
Preliminary Data Sheet
The following diagram illustrates the relationship among the signals involved with a DDR write operation.
Figure 7. DDR SDRAM Write Cycle Timing
PLB Clk
MemClkOut
T_SA
Addr/Cmd
T_SK
T_HA
T_DS
T_DS
DQS
MemData
T_SD
T_SD
T_HD
T_HD
T_SK = Delay from rising edge of MemClkOut to rising/falling edge of signal (skew)
T_SA = Setup time for address and command signals to MemClkOut
T_HA = Hold time for address and command signals from MemClkOut
T_SD = Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
T_HD = Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
T_DS = Delay from rising/falling edge of clock to the rising/falling edge of DQS
Note: The timing data in the following tables is based on simulation runs using Einstimer.
Table 21. I/O Timing—DDR SDRAM T_DS
Notes:
1. All of the DQS signals are referenced to MemClkOut with the DQS delay line programmed to 1 cycle.
2. Clock speed is 200MHz.
DQS0
DQS1
DQS2
DQS3
DQS4
Signal Name
Minimum
4
4
4
4
4
T_DS (ns)
Maximum
6
6
6
6
6
60
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