405EX Datasheet, PDF (62/67 Pages) Applied Micro Circuits Corporation – PowerPC 405EX Embedded Processor

PPC405EX – PowerPC 405EX Embedded Processor
Revision 1.09 - August 21, 2007
Preliminary Data Sheet
Figure 8. DDR SDRAM Read Data Path
Ext FeedBack
Signals
MemDCFdbkD ^Driver
Coarse Delay
DDR 1X Clock
FeedBack
Signal Gen ^{CAS Lat Delay}
Read Start
FF: Flip-Flop
Rec
MemDCFdbkR
Fine Delay
Feedback
Data Capture
Window
DQS aligned
FBK signal
DDR 1X Clock
Stage 2 Store
Cycles +1
Delay
T1 T2 T3 T4
Oversampling
Fine Delay
Read Latency adjust circuit
Package
pins
0
1
Mux
DQ
Data
(x32)
adjust
7
Q2_Ovs
0
FF
2
4
6
FF
FF
D
Q2
Compare
(x32)
Mux
C
DQS Rising
Edge Sync
Stage 1
Stage 2
Oversampling
Clock
Read FIFO
Upper
PLB bus
[0:63]
Lower
Stage 3
FF
1
3
5
7
FF
FF
D
C
(x32)
FF ^{Q3 PLB bus}
[64:127]
DQS
Programmed
Read DQS
Delay
DQS Falling
Edge Sync
DDR 1X Clock
PLB 1X Clock
DDR SDRAM Read Cycle Timing
The following diagram illustrates the relationship of the signals involved with a DDR read operation.
Figure 9. DDR SDRAM Memory Data and DQS
DQS
T_SD
MemData
T_HD
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