405EX Datasheet, PDF (43/67 Pages) Applied Micro Circuits Corporation – PowerPC 405EX Embedded Processor

PPC405EX – PowerPC 405EX Embedded Processor
Revision 1.09 - August 21, 2007
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 6 of 7)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Description
I/O
Type
S_VREF1A:B
S_VREF2A:B
DDR 1 (DDR2) Reference voltage 1 and 2 inputs:
Min. +1.15 (+0.825)V
Nom. +1.25 (+0.9)V
Max. +1.35 (0.975)V
Serial Communication Port (SCP) Interface
I
1.25V (0.9V)
Volt ref receiver
SCPClkOut
Output clock.
SCPDI
Data input.
SCPDO
Data output.
UART Peripheral Interface
The UART interface can be configured as follows:
1. One 8-pin
2. Two 4-pin
3. Two 2-pin (pull up DCD, DSR, CTS and RTS)
4. One 4-pin and one 2-pin
UARTSerClk
Serial clock input.
UARTnCTS
UARTnDCD
UARTnDSR
UARTnDTR
UARTnRI
UARTnRTS
Clear to send.
Data carrier detect.
Data set ready.
Data terminal ready.
Ring indicator.
Request to send.
UARTnRx
Receive data.
I/O 3.3V LVTTL
I
3.3V LVTTL
O
3.3V LVTTL
3.3V LVTTL
I
receiver
w/pull-up
I/O 3.3V LVTTL
I/O 3.3V LVTTL
I/O 3.3V LVTTL
I/O 3.3V LVTTL
I/O 3.3V LVTTL
I/O 3.3V LVTTL
3.3V LVTTL
I
receiver
w/pull-down
UARTnTx
USB 2.0 Interface
Transmit data.
O
3.3V LVTTL
USB2Clk
USB clock.
I
3.3V LVTTL
receiver
USB2Data0:7
USB2Dir
USB2Next
USB2Stop
Parallel data bus.
I/O 3.3V LVTTL
Data bus direction control.
I/O 3.3V LVTTL
Next data byte control. When data is being transferred to the PHY,
the next byte should be sent. When data is being received from the
I/O
3.3V LVTTL
PHY, the next byte is available.
Stop output control.
I/O 3.3V LVTTL
Notes
1, 6
1, 6
1, 6
1
1
1
5
AMCC Proprietary
43