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405EX Datasheet, PDF (11/67 Pages) Applied Micro Circuits Corporation – PowerPC 405EX Embedded Processor | |||
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PPC405EX â PowerPC 405EX Embedded Processor
Revision 1.09 - August 21, 2007
Preliminary Data Sheet
⢠PCI-Express to PCI-Express opaque (Non-Transparent) bridge
⢠Power Management
⢠Supports one virtual channel (VC0) with no Traffic Class (TC) filtering
⢠Maximum Payload block size 256B
⢠Supports up to 512B maximum Read request size
⢠Requests supported:
â Up to two posted outbound Write requests (memory and messages)
â Up to two posted inbound Write requests
â Up to two outbound Read requests outstanding on PCI Express
â Up to two inbound Read requests outstanding on PCI Express
â Outbound I/O request as a PCI Express Root Port
â Inbound I/O request as a PCI Express End Point
⢠Buffering in each PCI Express Port for the following transaction types:
â 1KB Replay buffer: up to eight in flight transactions
â 512B for Outbound posted Writes
â 512B for Outbound Reads completion
â 512B for Inbound posted Writes
â 512B for Inbound Reads completion
⢠Parity checking on each buffer
⢠POM Programmable Outbound Memory Regions: 3 Memory, 1 I/O, 1 Message, 1 config, 1 Internal Regs
⢠PIM Programmable Inbound Memory Regions: 4 Memory, 1 I/O, 1 Expansion ROM
⢠INTx Interrupts support (PCI legacy):
â Up to four INTx Termination for Root Ports. A/B/C/D interrupts are wired to the UIC
â A/B/C/D INTx types Generation for Endpoints
⢠MSI - Message Signaled Interrupts
â MSI Generation for End Point
â MSI Termination for Root Ports
â MSI_X Termination for Root Ports
Security Function
The built-in security function is a cryptographic engine attached to the 128-bit PLB with built-in DMA and interrupt
controllers.
Features include:
⢠Federal Information Processing Standard (FIPS) 140-2 design
⢠Support for an unlimited number of Security Associations (SA)
⢠Different SA formats for each supported protocol (IPsec, SSL/TLS/DTLS, MACSec, SGT L2/L3 and sRTP)
⢠Internet Protocol Security (IPSec) features
â Full packet transforms (ESP & AH)
â Complete header and trailer processing (IPv4 and IPv6)
â Multi-mode automatic padding
â "Mutable bit" handler for AH, including IPv4 option and IPv6 extension headers
⢠Secure Socket Layer (SSL), Transport Layer Security (TLS), and Datagram Transport Layer Security (DTLS)
â Packet transforms
â One-pass hash-then-encrypt or decrypt-then-hash for SSL, TLS and DTLS packet transforms using ARC4
Stream Cipher
⢠Secure Real-Time Protocol (sRTP) features
â Packet transforms
â ROC removal and TAG insertion
â Variable bypass offset of header length per packet
AMCC Proprietary
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