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405EX Datasheet, PDF (10/67 Pages) Applied Micro Circuits Corporation – PowerPC 405EX Embedded Processor | |||
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PPC405EX â PowerPC 405EX Embedded Processor
Revision 1.09 - August 21, 2007
Preliminary Data Sheet
Features include:
⢠Memory-to-memory transfers
⢠Buffered memory-to-peripheral transfers
⢠Buffered peripheral-to-memory transfers
⢠Four independent DMA channels
⢠Scatter/gather capability for dynamically programming multiple DMA transfers
⢠Programmable address increment or decrement
⢠Internal data buffering
⢠Can transfer data to/from any PLB slave, including the external bus
USB 2.0 OTG Interface
One USB 2.0 On-the-Go (OTG) controller that can be configured as either a Host or Device port.
Features include:
⢠Low- (Host only), Full- and High-Speed support
⢠Internal DMA to optimize performance and offload the CPU
⢠Up to two IN/OUT Endpoints in Device mode (one can be isochronous)
⢠Supports maximum packet size of 1024B (isochronous) and 512B (bulk)
⢠Support for isochronous traffic
⢠Three packets per microframe (24MB/s throughput)
⢠Eight KB buffer
⢠ULPI SDR interface
DDR1/2 SDRAM Controller
The Double Data Rate 1/2 (DDR1/2) SDRAM memory controller supports industry standard discrete devices that
are compatible with both the DDR1 or DDR2 specifications. The correct I/O supply voltage must be provided for the
two types of DDR devices: DDR1 devices require +2.5V and DDR2 devices require +1.8V.
Global memory timings, address and bank sizes, and memory addressing modes are programmable.
Features include:
⢠16- or 32-bit memory interface
⢠Optional 8-bit error checking and correcting (ECC)
⢠1.6-GB/s peak data rate
⢠Two memory banks of up to 1 GB each
⢠Maximum capacity of 2GB
⢠Support for one memory bank of 2GB with CAS latencies of 2, 2.5, or 3
⢠Clock frequencies from 133MHz (266Mbps) to 200MHz (400Mbps) supported
(Faster parts may be used, but must be clocked no faster than 200MHz)
⢠Page mode accesses (up to 16 open pages) with configurable paging policy
⢠Programmable address mapping and timing
⢠Software initiated self-refresh
⢠Power management (self-refresh, suspend)
⢠Two regions (two chip selects, one clock driver)
PCI Express
The PCI Express single-lane interfaces include the following features:
Features include:
⢠Compliant with PCI Express base specification 1.1
⢠Each PCI Express port can be End Point or Root Complex. (Upstream & Downstream)
â Applications compliant with MSI rules are limited to one End Point port per PPC405EX
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AMCC Proprietary
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