405EX Datasheet, PDF (13/67 Pages) Applied Micro Circuits Corporation – PowerPC 405EX Embedded Processor

PPC405EX – PowerPC 405EX Embedded Processor
Revision 1.09 - August 21, 2007
Preliminary Data Sheet
• Independently controlled transmit, receive, line status, and data set interrupts
• Programmable baud generator (divides serial clock input and generates 16x clock)
• Ability to add/delete standard asynchronous communication bits such as start, stop, and parity to/from serial
data
• Even, odd, or no-parity bit generation and detection
• Stop bit generation of 1, 1.5, or 2 bits
• Variable baud rate
• Internal diagnostic capability
• Loopback controls for isolating communications link faults
• Break, parity, overrun, framing error simulation
• OPB interface with optional DMA support
IIC Bus Interface
The Inter-Integrated Circuit (IIC) interface provides a Philips I²C^® compatible interface operating up to 400kHz
either as a master, a slave, or both with a bootstrap controller (BSC) included. During chip reset, the bootstrap
controller can read configuration data from an IIC compatible memory device (e.g., EEPROM). This data can be
used to replace the default configuration settings provided by the chip.
Features include:
• Two IIC channels
• Compliant with Philips Semiconductors I²C Specification, dated 1995
• Operation at 100kHz or 400kHz
• Byte (8-bit) data
• Addresses are 10 or 7 bits
• Slave Transmit and Receive
• Master Transmit and Receive
• Multiple bus masters supported
• Programmable as master, slave, or master/slave
• Boot parameters read from IIC attached memory (Port 0) with IIC bootstrap controller
• OPB slave interface is 32 bits wide
Serial Communication Port Interface (SCP/SPI)
The Serial Communication Port (SCP) (also known as the Serial Peripheral Interface or SPI) is a full-duplex,
synchronous, character-oriented (byte) port that allows the exchange of data with other serial devices. The SCP is
a master on the serial port supporting a three-wire interface (receive, transmit, and clock), and is a slave on the
OPB.
Features include:
• One SCP channel, full duplex synchronous
• SCP master
• Up to 25MHz
• Programmable internal loopback capabilities
• Multi-master protocol supported
• Independent masking of all interrupts (master collision, transmit FIFO overflow, transmit FIFO empty, receive
FIFO full, receive FIFO underflow, receive FIFO overflow)
• Dynamic control of serial bit rate of data transfer (serial-master mode only)
• Data Item size for each data transfer under programmer control (4-to-16 bits)
• OPB slave interface is 32 bits wide
AMCC Proprietary
13