405EX Datasheet, PDF (5/67 Pages) Applied Micro Circuits Corporation – PowerPC 405EX Embedded Processor

PPC405EX – PowerPC 405EX Embedded Processor
Block Diagram
Revision 1.09 - August 21, 2007
Preliminary Data Sheet
Figure 1. PPC405EX Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
x3
Clock
Control
Reset
Power
Mgmt
Timers
MMU
Power PC
405 Processor
JTAG
Trace
16KB D-Cache 16KB I-Cache
DCRs
DCR
Bus
Arbiter
NAND
UART
x2
IICx2/
BSC
SCP
(SPI)
GPIO
Flash EBC
Controller
EBM
On-chip Peripheral Bus (OPB)
OPB/PLB
Bridges
GPT
PKA
TRNG
Arbiter
Processor Local Bus (PLB4)—128 bits
DDR1/2
SDRAM
Controller
EIP-94
Security
Feature
PCI-E PCI-E
1-lane 1-lane
DMA
Controller
(4-Channel)
MAL/w
Interrupt Coalescing
HSS HSS
Ethernet
MAC
1 Gbit
x2
AHB-PLB
Bridge
USB 2.0
OTG
Controller
ULPI
The PPC405EX is designed using the IBM Microelectronics Blue Logic^TM methodology in which major functional
blocks are integrated together to create an ASIC (application-specific integrated circuit) product. This approach
provides a consistent way to create complex ASICs using IBM CoreConnect^TM Bus Architecture.
AMCC Proprietary
5