405EX Datasheet, PDF (39/67 Pages) Applied Micro Circuits Corporation – PowerPC 405EX Embedded Processor

PPC405EX – PowerPC 405EX Embedded Processor
Revision 1.09 - August 21, 2007
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 2 of 7)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Description
I/O
Type
PCI Express Interface (n = 0 and 1)
PCIEnATB
Analog Test Bus for manufacturing test.
O
CML
PCIEnClkC
PCIEnClkT
PCIEnRExt
PCIEnRExtG
Differential input for external reference clock.
I
External reference resistor. Attach a 1.37 kΩ, 1% resistor between
RExt and RExtG to provide the reference for both the bias currents
I/O
and the impedance calibration circuitry.
CML
CML
PCIEnRx
PCIEnRx
Differential receiver for received serial data.
I LVDS receiver
PCIEnTx
PCIEnTx
Differential driver for transmitted serial data.
O
LVDS driver
Interrupts Interface
IRQ0:2
External interrupt requests.
I/O 3.3V LVTTL
IRQ3:5
IRQ6
External interrupt requests.
External interrupt requests.
I/O 3.3V LVTTL
I/O 3.3V LVTTL
IRQ7:9
JTAG Interface
External interrupt requests.
I/O 3.3V LVTTL
TCK
TDI
TDO
Test clock.
Test data in.
Test data out.
I
3.3V LVTTL
I
3.3V LVTTL
w/pull-up
O
3.3V LVTTL
TMS
TRST
Test mode select.
I
3.3V LVTTL
w/pull-up
Test reset. Must be low at power-on to initialize the JTAG controller
and for normal operation of the PPC405EX.
I
3.3V LVTTL
w/pull-up
Notes
5
1, 5
5
1, 5
1
1, 4
1
1, 5
AMCC Proprietary
39