405EX Datasheet, PDF (61/67 Pages) Applied Micro Circuits Corporation – PowerPC 405EX Embedded Processor

PPC405EX – PowerPC 405EX Embedded Processor
Revision 1.09 - August 21, 2007
Preliminary Data Sheet
Table 22. I/O Timing—DDR SDRAM T_SK, T_SA, and T_HA
Signal Name
MemAddr00:14
BA0:2
BankSel0:1
MemClkEn
CAS
RAS
WE
T_SK (ns)
Minimum
Maximum
0.20
0.20
T_SA (ns)
Minimum
+2.3
T_HA (ns)
Minimum
+2.3
Table 23. I/O Timing—DDR SDRAM Write TimingT_SD and T_HD
Notes:
1. T_SD and T_HD are measured under worst case conditions.
2. Clock speed for the values in the table is 200MHz.
3. The time values in the table include 1/4 of a cycle at 200MHz (5ns x 0.25 = 1.25 ns).
4. To obtain adjusted T_SD and T_HD values for lower clock frequencies, subtract 1.5 ns from the values in the table and add 1/4
of the cycle time for the lower clock frequency (for example, T_SD − 1.25 + 0.25T_CYC).
Signal Names
MemData00:07, DM0
MemData08:15, DM1
MemData16:23, DM2
MemData24:31, DM3
ECC0:7, DM4
Reference Signal
DQS0
DQS1
DQS2
DQS3
DQS4
T_SD (ns)
0.84
0.84
0.84
0.84
0.84
T_HD (ns)
1.15
1.15
1.15
1.15
1.15
DDR SDRAM Read Operation
The Read of the incoming Data from the SDRAM is done on the rising and falling edges of the differential DQS
signal. The Data must be centered to these edges for correct operation.
The PPC405EX can delay with very fine granularity the DQS through register programming.
DDR SDRAM MemClkOut0 and Read Clock Delay
In order to accommodate timing variations introduced by the system designs using this chip, the three-stage data
path shown below is used to eliminate metastability and allow data sampling to be adjusted for minimum latency.
The data is stored in the eight Flip Flops of the Stage 1, such that it can be transferred later within a 8x period.
AMCC Proprietary
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