AK4601VQ Datasheet, PDF (66/111 Pages) Asahi Kasei Microsystems – Audio HUB CODEC with Digital Mixer

[AK4601]
4. Clock Reset
When CKRESETN bit = “0” after power-down mode is released (PDN pin = “H”), the AK4601 is in clock
reset state. All blocks except the power supply circuits for REF generation and digital circuits are in
power-save mode. Even the internal PLL for master clock generation is powered down.
Control register settings should be made with an interval of 1ms (min) or more after releasing the
power-down mode.
Necessary system clocks (Table 4, Table 5) should be input before the clock reset is released. The
internal PLL starts operation and the master clock is generated when clock reset is released
(CKRESETN bit = “1”) (Figure 52). The AK4601 will be in operation by releasing power-down mode of
the blocks by setting each power-management bit.
System clocks must be changed during clock reset or in power-down mode (PDN pin = “L”). The PLL
and the internal clocks are stopped by this clock reset and the clock change can be done safely. Change
register settings and system clock frequencies during the clock reset. After system clock is stabilized, the
PLL starts operation by setting CKRESETN bit to “1”.
Clock operated blocks (ADC and DAC) must be powered down before executing clock reset. These
blocks can be powered down simultaneously by setting HRESETN bit to “0” from “1” (each PMAD and
PMDA bits settings are not necessary). Set HRESETN bit to “1” from “0” with an interval of 10ms for
stabilization of PLL after clock reset is released.
MCKI
BICK1
PLLREF Mode 0
PLLREF Mode 1
CSN
SCLK (Simplified)
SI
C0 00 84 00
HRESETN bit
C0 00 01 00
C0 00 00 29 87
C0 00 84 0F
CKRESETN bit
Blocks except PLL
are stopped
PLL Stop
Input clock and clock mode can be changed
PLL Stabilize
Resume
Operation
Figure 53. Clock Mode Switching Sequence
016000391-E-01
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2016/12