AK4601VQ Datasheet, PDF (37/111 Pages) Asahi Kasei Microsystems – Audio HUB CODEC with Digital Mixer

[AK4601]
2-2. Clock Sync Domain
The AK4601 has two Clock Sync Domains (SD1-2). Reference clocks (LRCKSDx, BICKSDx, x=1~2)are
output according to each register settings for SD1-2 (Figure 14). The internal audio data and input/output
data of the AK4601 must be synchronized with one of these two Clock Sync Domains.
When MSNx bit =“0”, input pins (LRCKx pin/BICKx pin) are selected for the clock sync reference clock.
When MSNx bit = “1”, internal dividing clocks (MLRCKx/MBICKx) are selected for the clock sync
reference clock (Table 7).
MSNx bit Reference Clock (LRCKSDx/BICKSDx)
0
Input Pin (LRCKx pin/BICKx pin)
Internal Dividing Clock (MLRCKx/MBICKx)
1
Reference clock is generated internally by
CKSx[2:0], BDVx[8:0] and SDVx[2:0] bits settings.
Table 7. Reference Clock of Clock Sync Domain
PLL_MCLK
MCKI
BICK1~2
BICK1 pin
LRCK1 pin
CKS1[2:0]
DIV
BDV1[8:0]
MBICK1
DIV
SDV1[2:0]
MLRCK1
BICK2 pin
LRCK2 pin
CKS2[2:0] / BDV2[8:0] / SDV2[2:0]
Figure 14. Clock Sync Domain
BICK_SD1
LRCK_SD1
MSN1
BICK_SD2
LRCK_SD2
MSN2
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2016/12