AK4601VQ Datasheet, PDF (43/111 Pages) Asahi Kasei Microsystems – Audio HUB CODEC with Digital Mixer

[AK4601]
2-4. CLKO Pin Output Clock
The CLKO pin of the AK4601 outputs a divided clock of PLL MCLK. The output frequency setting of the
CLKO pin is controlled by CLKOSEL[2:0] bits (Table 13).
CLKOSEL[2:0]
bits
000
001
010
011
100
101
Output Frequency
(fs=48kHz base)
Output Frequency
(fs=44.1kHz base)
12.288MHz
11.2896MHz
24.576MHz
22.5792MHz
8.192MHz
7.5264MHz
6.144MHz
5.6448MHz
4.096MHz
3.7632MHz
2.048MHz
1.8816MHz
Table 13. CLKO Pin Setting
(default)
2-5. BICK2/SDIN3 pin and LRCK2/SDOUT3 pin Settings
Pin functions of the BICK2/SDIN3 pin and the LRCK2/SDOUT3 pin are selected by MSELN bit. When
MSELN bit is “0”, the BICK2/SDIN3 pin works as the BICK2 pin and the LRCK2/SDOUT3 pin works as
the LRCK2 pin. When MSELN bit is “1”, the BICK2/SDIN3 pin works as the SDIN3 pin and the
LRCK2/SDOUT3 pin works as the SDOUT3 pin.
MSELN bit
Function
0
BICK2
(default)
1
SDIN3
Table 14. BICK2/SDIN3 Pin Setting 1
2-6. SDINx/BICKx/LRCKx Pin Setting
The AK4601 has three SDIN pins and two BICK/LRCK pins. They are independent each other.
Synchronized channel of the SDINx pin can be selected by EXBCKx[2:0] bits from BICKx pin and
LRCKx pin (Table 15).
EXBCKx[2:0] bits
BICK and LRCK pins that
synchronizes to SDINx pin
000
TieLow
(default)
001
BICK1 pin, LRCK1 pin
010
BICK2 pin, LRCK2 pin
011
100
101
N/A
110
111
Table 15. BICKx/LRCKx pin Setting for Synchronization to SDINx pin
MSNx bit selects Master/Slave mode of the BICKx pin and the LRCKx pin. (Table 16)
MSNx bit
BICKx pin, LRCKx pin
0
Slave Mode (Input)
1
Master Mode (Output)
Table 16. BICKx pin/LRCKx pin Mode Select
(default)
016000391-E-01
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2016/12