AK4601VQ Datasheet, PDF (45/111 Pages) Asahi Kasei Microsystems – Audio HUB CODEC with Digital Mixer

[AK4601]
■ Data Path Setting
1. Data Bus, In/Output Port
The AK4601 has a 32-bit serial audio stereo data bus (Figure 17). Inputs and outputs of each internal
block and all input/output pins of the AK4601 are connected to this serial audio data bus. The port that
data is input to this serial audio data bus is defined as “input port” and the port that data is output from
the audio data bus is defined as “output port”. Each port selects Clock Sync Domain and inputs (outputs)
audio data that synchronized to the reference clock of the Clock Sync domain to the data bus (Figure
17).
A stereo data on each port is defined as “data source”. All data sources are connected to the serial audio
bus and a data source on any input port can be output from any output port. Data connection of the data
bus and a data port with the same sampling frequency is defined as “data path”. Input and output ports
on the same data path should have the same Clock Sync Domain. If these ports have different Clock
Sync Domains, reference clocks (BICK SDx, LRCK SDx) must be synchronized and the sampling
frequency must be the same. Phase synchronization of reference clocks is not necessary if the
frequency of these clocks are synchronized. However, frequencies of BICK SDx can be different.
An SRC is necessary for data transmission between two ports that have clock sync domain with different
sampling frequencies or different reference clocks.
SDIN1pin
SDIN2pin
SDIN3pin
SDOUT1pin
SDOUT2pin
SDOUT3pin
VOL1
VOL2
VOL3
SDIN1
SDIN1
SDIN2
SDIN1
SDIN3
: Input Port
SDIN1
SDOUT1～ ^{: Output Port}
: Sync free
5
ADC1
SDIN1
ADC1
ADC2
SDIN1
ADC2
SD^SDO^OU^UT^T1¹ï½ž
SD^SDO^OU5^UT^T1²ï½ž
SD^SDO^OU5^UT^T1³ï½ž
5
SD^VO^OU^LT^I11～
VOLO1
SD5IN1
VOLI2
SDOUT1～
VOLO2
SD5IN1
SD^VO^OU^LT^I31～
VOLO3
SD5IN1
ADCM
SDIN1
ADCM
MIXAI1
SDOUT1～
SD_MMOU_II5XXAAT_OI1²ï½ž
SD5IN1
MIXBI1
SDOUT1～
SD_MMOU_II5XXBBT_OI1²ï½ž
SD5IN1
MIXER A
MIXER B
“0” data
DAC1
SDOUT1～
DA⁵C2
SDOUT1～
DA⁵C3
SDOUT1～
0x00⁵00 0000
DAC1
DAC2
DAC3
Data Bus
Figure 17. Data Path, Input/Output Port
016000391-E-01
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2016/12