AK4601VQ Datasheet, PDF (38/111 Pages) Asahi Kasei Microsystems – Audio HUB CODEC with Digital Mixer

[AK4601]
The clock source of Internal dividing clock MBICKx is selected by CKSx[2:0] bits (Table 8). MBICKx is
generated by dividing the selected clock source according to the BDVx[8:0] bits setting (Table 9).
Additionally, MLRCKx is generated by dividing this MBICKx by setting SDVx[2:0] bits (Table 8).
CKSx[2:0] bits
Clock Source
000
TieLow
(default)
001
PLL MCLK
010
MCKI
011
BICK1
100
BICK2
Others
N/A
Table 8. Clock Source of Internal Dividing Clock
BDVx[8:0] bits
Divide by
0x00
1
0x01 – 0xFF
BDVx+1
Table 9. MBICKx Setting
(default)
SDVx[2:0] bits
Divide by
000
64
(default)
001
48
010
32
011
128
100
256
101
N/A
110
N/A
111
512
Table 10. MLRCKx Setting (N/A: Not available)
Clock Sync Domain settings when PLL MCLK is selected as the clock source are shown in Table 11.
PLL MCLK = 122.88MHz (48kHz base) / 112.896MHz (44.1kHz base)
MBICKx = PLL MCLK dvided by BDVx[8:0] bits setting
MLRCKx = MBICKx divided by SDVx[2:0] bits setting
e.g.) MBICKx= 122.88MHz/240= 0.512MHz, MLRCKx= 0.512MHz/64= 8kHz when PLL_MCLK =
122.88MHz (fs=48kHz), BDVx[8:0] bits= “0xEF”(divide by 240) and SDVx[2:0] bits = “000” (divide
by 64).
016000391-E-01
- 38 -
2016/12