AK4601VQ Datasheet, PDF (39/111 Pages) Asahi Kasei Microsystems – Audio HUB CODEC with Digital Mixer

[AK4601]
When PLL_MCLK is selected as the clock source, frequency settings other than shown in Table 11 are
not available.
BDVx[8:0] BDVx[8:0] bits
bits
Dividing
MBICKx(MHz)
48kHz 44.1kHz
base
base
SDVx[2:0]
bits
SDVx[2:0]
bits
Dividing
MLRCKx(kHz)
48kHz 44.1kHz
base base
0x1DF
480
0.256 0.2352
010
32
8
-
0x13F
320
0.384 0.3528
001
48
8
-
0x0EF
240
0.512 0.4704
000
64
8
-
0x077
120
1.024 0.9408
011
128
8
-
0x03B
60
2.048 1.8816
100
256
8
-
0x01D
30
4.096 3.7632
111
512
8
-
0x13F
320
0.384 0.3528
010
32
12
11.025
0x09F
160
0.768 0.7056
000
64
12
11.025
0x04F
80
1.536 1.4112
011
128
12
11.025
0x027
40
3.072 2.8224
100
256
12
11.025
0x013
20
6.144 5.6448
111
512
12
11.025
0x0EF
240
0.512 0.4704
010
32
16
14.7
0x09F
160
0.768 0.7056
001
48
16
14.7
0x077
120
1.024 0.9408
000
64
16
14.7
0x03B
60
2.048 1.8816
011
128
16
14.7
0x01D
30
4.096 3.7632
100
256
16
14.7
0x00E
15
8.192 7.5264
111
512
16
14.7
0x09F
160
0.768 0.7056
010
32
24
22.050
0x04F
80
1.536 1.4112
000
64
24
22.050
0x027
40
3.072 2.8224
011
128
24
22.050
0x013
20
6.144 5.6448
100
256
24
22.050
0x009
10
12.288 11.2896
111
512
24
22.050
0x077
120
1.024 0.9408
010
32
32
29.4
0x04F
80
1.536 1.4112
001
48
32
29.4
0x03B
60
2.048 1.8816
000
64
32
29.4
0x01D
30
4.096 3.7632
011
128
32
29.4
0x00E
15
8.192 7.5264
100
256
32
29.4
0x04F
80
1.536 1.4112
010
32
48
44.1
0x027
40
3.072 2.8224
000
64
48
44.1
0x013
20
6.144 5.6448
011
128
48
44.1
0x009
10
12.288 11.2896
100
256
48
44.1
0x004
5
24.576 22.5792
111
512
48
44.1
0x027
40
3.072 2.8224
010
32
96
88.2
0x013
20
6.144 5.6448
000
64
96
88.2
0x009
10
12.288 11.2896
011
128
96
88.2
0x004
5
24.576 22.5792
100
256
96
88.2
0x013
20
6.144 5.6448
010
32
192
176.4
0x009
10
12.288 11.2896
000
64
192
176.4
0x004
5
24.576 22.5792
011
128
192
176.4
Table 11. Clock Sync Domain Setting when PLL MCLK is Clock Source
For Clock Sync Domain, set BDVx[8:0] bits and SDVx[2:0] bits according to the input clock frequency
when the MCKI or BICK pin input is selected as the clock source, as well as the PLL MCLK.
MBICKx= MCKI pin or BICKx pin frequency divided by BDVx[8:0] bits setting
MLRCKx= MBICKx divided by SDVx[2:0] bits setting
016000391-E-01
- 39 -
2016/12